CHALLENGE
Our customer is an extremely ambitious start-up that aims at redefining fingerprint sensing by merging the high quality of capacitive sensing with the benefits of TFT technology (cost, size, integrability, conformability). They decided to prove it on the largest Fingerprint Acquisition Format (FAP) defined by the FBI Appendix-F biometrics acquisition standard, the FAP60, and bypass all the smaller formats. They wanted to build a capacitive fingerprint scanner using Sharp’s TFT technology, so they designed an embedded fingerprint acquisition system, but a fundamental piece was missing: a Read-Out IC (ROIC) to bridge the analog domain of the TFT matrix and the digital domain of data processing.
The dynamic needs of a start-up customer, the high degree of innovation inherent to this project, and the additional design constraint from the intended Chip-on-Foil (CoF) post-processing, called for an adaptable design partner with first-time-right mindset, and SystematIC accepted the challenge.
SOLUTION
SystematIC designed a ROIC with TFT drivers according to our customer’s specifications. We succeeded in designing a modular stack of 400 compact read-out channels with 10-bit digital output and 10-μs conversion time. Moreover, we designed an auxiliary array of high-voltage drivers for the TFT matrix addressing.
The channel pitch matches the tight requirement of the application, which is key to minimize the IC area (competitor’s products of similar number of channels take up to twice as much silicon area). This is possible thanks to the efficient use and careful design of medium-high-accuracy data converters, where part of the resources is shared among the channels.
The fast line conversion time, in combination with pipeline operation and a dedicated parallel output data line bus (LVDS compatible, 5 physical channels), are essential to achieve a full frame scan in less than 60 ms, for the largest fingerprint acquisition format (FAP60).
The ROIC timing is provided by an external host, which allows for fast and flexible evaluation of the first samples and reduces the chances of design mistakes. The host receives the converted data and reassembles the fingerprint image line by line.
TIME
We assisted our client for its very first product development with first-time-right silicon design and layout for an effective period of 9 months, followed by measurement support that significantly reduced the time needed to reach the intended system performance.
WE ARE PROUD
To meet customer’s expectations with a first-time-right design prototype, thanks to our pool of skilled designers and our scrupulous approach to address every possible source of failure at an early stage. To believe in the customer’s vision of a new fingerprint sensing paradigm and persevere when the design poses unexpected challenges. To share the customer’s enthusiasm when they finally unlock the excellent fingerprint picture quality that our ROIC can deliver.
BENEFITS FOR CUSTOMER
- First-time-right prototype design saved significant extra development time and cost, a key benefit for a start-up customer.
- Customer could show the first functional FAP60 capacitive TFT fingerprint sensor ever made at CES 24 in Las Vegas.
- All key performances met the initial expectations and enabled a seamless upgrade of the prototype design to a product.
- A highly modular design that can be rapidly adapted to different FAP requirements.
- IC area 50% smaller than solutions available at the time of development with a comparable number of channels, thanks to an optimized read-out channel design.
- Precision analog and mixed-signal design techniques to reach target resolution (10 bit).
- Compatibility with ultra-fine-pitch CoF post-processing to prevent pad-limited layout.
- Clear design report and application datasheet for full customer support.
- 400 parallel read-out channels.
- 10-bit resolution.
- Pipeline readout operation.
- Low channel current consumption (50 μA).
- 24-V drivers for TFT matrix line selection.
- 60-ms full frame scan time for FAP60 profile (1500 rows x 1600 columns).
- 5 DDR, LVDS-compatible output data lines for fast data acquisition.
- Fine channel pitch (20 μm) to minimize silicon area (~10 mm2)
- Low-resolution modes for compatibility with different fingerprint acquisition profiles.
- 130-nm BCD process
- Compatible with gold bump post-processing for fine-pitch CoF
OUR OTHER SUCCESS STORIES
IC solutions that are tailor made for you can help you achieve your business goals.
SystematIC was founded to help businesses envision, plan, and develop such custom IC solutions.
